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| Architecture: Type : Last Update: | Flash Memory Components Bulk Erase Simulation Models 6/26/97 11:30:00 AM | Vendor Information |
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Logic Modeling produces both SmartModels (behavioral models that operate in most simulation environments including both VHDL and Verilog) and SourceModels (explicit VHDL or Verilog models comprised of the original source code). |
Tool Features:
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File Attachments:
Supported Device Detail Matrix:
| Part & Package | Revision | Status | Availability | ||||||
| 28F010 - PDIP-32 ld 28F010 - PLCC-32 ld 28F010 - TSOP-32 ld 28F010 - TSOP-32 ld(R) 28F020 - PDIP-32 ld 28F020 - PLCC-32 ld 28F020 - TSOP-32 ld 28F020 - TSOP-32 ld(R) | 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 | Released Released Released Released Released Released Released Released | NOW NOW NOW NOW NOW NOW NOW NOW |
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19500 NW Gibbs Drive |
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Fax : (503) 690-6906 |
Contact the vendor above for the latest Distributor information